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august 2011 doc id 019013 rev 3 1/13 13 STL8N65M5 n-channel 650 v, 0.56 ? , 7 a mdmesh? v power mosfet in powerflat? 5x5 features worldwide best r ds(on) * area higher v dss rating high dv/dt capability excellent switching performance easy to drive 100% avalanche tested applications switching applications description this device is an n-channel mdmesh? v power mosfet based on an innovative proprietary vertical process technology, which is combined with stmicroelectronics? well-known powermesh? horizontal layout structure. the resulting product has extremely low on- resistance, which is unmatched among silicon- based power mosfets, making it especially suitable for applications which require superior power density and outstanding efficiency. figure 1. internal schematic diagram order code v dss @ t jmax r ds(on) max i d STL8N65M5 710 v < 0.6 ? 7 a (1) 1. the value is rated according to r thj-case powerflat? 5x5 1 2 3 4 12 1 3 14 7 6 5 11 10 9 8 pin 1 dr a in s 2 s 3 s 4 (not connected) d 14 d 1 3 d 12 11 g 10 s 9 s 8 s 5 d 6 d 7 d table 1. device summary order code marking package packaging STL8N65M5 8n65m5 powerflat? 5x5 tape and reel www.st.com
contents STL8N65M5 2/13 doc id 019013 rev 3 contents 1 electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 3 test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
STL8N65M5 electrical ratings doc id 019013 rev 3 3/13 1 electrical ratings table 2. absolute maximum ratings symbol parameter value unit v ds drain-source voltage (v gs = 0) 650 v v gs gate-source voltage 25 v i d (1) 1. the value is rated according to r thj-case drain current (continuous) at t c = 25 c 7 a i d (1) drain current (continuous) at t c = 100 c 4.4 a i d (2) 2. when mounted on fr-4 board of inch2, 2oz cu drain current (continuous) at t amb = 25 c 1.4 a i d (2) drain current (continuous) at t amb = 100 c 0.6 a i dm (2),(3) 3. pulse with limited by safe operating area. drain current (pulsed) 5.6 a p tot (2) total dissipation at t amb = 25 c 2.5 w p tot (1) total dissipation at t c = 25 c 70 w i ar avalanche current, repetitive or not- repetitive (pulse width limited by t j max) 2a e as single pulse avalanche energy (starting t j = 25 c, i d = i ar , v dd = 50 v) 120 mj dv/dt (4) 4. i sd 7 a, di/dt 400 a/s, v peak < v (br)dss , v dd = 400 v. peak diode recovery voltage slope 15 v/ns t stg storage temperature - 55 to 150 c t j max. operating junction temperature 150 c table 3. thermal data symbol parameter value unit r thj-case thermal resistance junction-case max 1.78 c/w r thj-pcb (1) 1. when mounted on 1inch2 fr-4 board, 2 oz cu thermal resistance junction-pcb max 60 c/w
electrical characteristics STL8N65M5 4/13 doc id 019013 rev 3 2 electrical characteristics (t c = 25 c unless otherwise specified) table 4. on /off states symbol parameter test conditions min. typ. max. unit v (br)dss drain-source breakdown voltage (v gs = 0) i d = 1 ma 650 v i dss zero gate voltage drain current (v gs = 0) v ds = 650 v v ds = 650 v, t c =125 c 1 100 a a i gss gate-body leakage current (v ds = 0) v gs = 25 v 100 na v gs(th) gate threshold voltage v ds = v gs , i d = 250 a 3 4 5 v r ds(on) static drain-source on resistance v gs = 10 v, i d = 3.5 a 0.56 0.6 ? table 5. dynamic symbol parameter test conditions min. typ. max. unit c iss c oss c rss input capacitance output capacitance reverse transfer capacitance v ds = 100 v, f = 1 mhz, v gs = 0 - 690 18 2 - pf pf pf c o(tr) (1) 1. c oss eq. time related is defined as a constant equival ent capacitance giving the sa me charging time as c oss when v ds increases from 0 to 80% v dss equivalent capacitance time related v ds = 0 to 520 v, v gs = 0 -17-pf c o(er) (2) 2. c oss eq. energy related is defined as a constant equivalent capacitance giving the same stored energy as c oss when v ds increases from 0 to 80% v dss equivalent capacitance energy related -52-pf r g intrinsic gate resistance f = 1 mhz open drain - 2.4 - ? q g q gs q gd total gate charge gate-source charge gate-drain charge v dd = 520 v, i d = 3.5 a, v gs = 10 v (see figure 15 ) - 15 3.6 6 - nc nc nc
STL8N65M5 electrical characteristics doc id 019013 rev 3 5/13 table 6. switching times symbol parameter test conditions min. typ. max unit t d(off) t r (v) t c(off) t f (i) turn-off delay time rise time cross time fall time v dd = 400 v, i d = 4 a, r g = 4.7 ?, v gs = 10 v (see figure 16 ), (see figure 19 ) - 50 14 20 11 - ns ns ns ns table 7. source drain diode symbol parameter test conditions min. typ. max. unit i sd i sdm (1) 1. pulse width limited by safe operating area source-drain current source-drain current (pulsed) - 7 28 a a v sd (2) 2. pulsed: pulse duration = 300 s, duty cycle 1.5% forward on voltage i sd = 7 a, v gs = 0 - 1.5 v t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd = 7a, di/dt = 100 a/s v dd = 100 v (see figure 16 ) - 200 1.6 16 ns c a t rr q rr i rrm reverse recovery time reverse recovery charge reverse recovery current i sd = 7 a, di/dt = 100 a/s v dd = 100 v, t j = 150 c (see figure 16 ) - 263 1.9 15 ns c a
electrical characteristics STL8N65M5 6/13 doc id 019013 rev 3 2.1 electrical characteristics (curves) figure 2. safe operating area figure 3. thermal impedance figure 4. output characteristics figure 5. transfer characteristics figure 6. gate charge vs gate-source voltage figure 7. static drain-source on resistance i d 1 0.1 0.01 0.001 0.1 1 100 v d s (v) 10 (a) oper a tion in thi s a re a i s limited b y m a x r d s (on) 10 s 100 s 1m s 10m s tj=150c tc=25c s ingle p u l s e 10 am07211v1 i d 6 4 2 0 0 10 v d s (v) (a) 5 15 8 10 5v 6v 7v v g s =10v 12 5.5v 6.5v 7.5v am0 8 197v1 i d 6 4 2 0 3 5 v g s (v) 7 (a) 4 6 8 8 10 12 9 v d s =20v am0 8 19 8 v1 v g s 6 4 2 0 0 5 q g (nc) (v) 8 10 15 10 v dd =520v i d = 3 .5a 12 3 00 200 100 0 400 500 v d s v g s am0 3 195v1 r d s (on) 0.56 0.54 0.52 0.50 0 4 i d (a) (ohm) 2 6 0.5 8 v g s =10v am0 8 200v1
STL8N65M5 electrical characteristics doc id 019013 rev 3 7/13 figure 8. capacitance variations figure 9. output capacitance stored energy figure 10. normalized gate threshold voltage vs temperature figure 11. normalized on resistance vs temperature figure 12. switching losses vs gate resistance (1) figure 13. normalized b vdss vs temperature 1. eon including reverse re covery of a sic diode c 1000 100 10 1 0.1 10 v d s (v) (pf) 1 100 ci ss co ss cr ss am0 8 202v1 e o ss 1.5 1.0 0.5 0 0 100 v d s (v) ( j) 400 2.0 200 3 00 2.5 3 .0 500 600 3 .5 am0 8 201v1 v g s (th) 1.00 0.90 0. 8 0 0.70 -50 0 t j (c) (norm) -25 1.10 75 25 50 100 am0 8 204v1 r d s (on) 2.0 1.5 0.5 -50 0 t j (c) (norm) -25 75 25 50 100 1.0 i d = 3 .5a v g s =10v am0 8 205v1 e 100 10 1 0 20 r g ( ? ) ( j) 10 3 0 40 i d =4a v cl =400v v g s =10v eon eoff am0 8 206v1 bv d ss -50 0 t j (c) (norm) -25 75 25 50 100 0.9 3 0.95 0.97 0.99 1.01 1.0 3 1.05 1.07 i d =1ma am0 8 20 3 v1
test circuits STL8N65M5 8/13 doc id 019013 rev 3 3 test circuits figure 14. switching times test circuit for resistive load figure 15. gate charge test circuit figure 16. test circuit for inductive load switching and diode recovery times figure 17. unclamped inductive load test circuit figure 18. unclamped inductive wavefor m figure 19. switching time waveform am0146 8 v1 v g s p w v d r g r l d.u.t. 2200 f 3 . 3 f v dd am01469v1 v dd 47k ? 1k ? 47k ? 2.7k ? 1k ? 12v v i =20v=v gmax 2200 f p w i g =con s t 100 ? 100nf d.u.t. v g am01470v1 a d d.u.t. s b g 25 ? a a b b r g g fa s t diode d s l=100 h f 3 . 3 1000 f v dd am01471v1 v i p w v d i d d.u.t. l 2200 f 3 . 3 f v dd am01472v1 v (br)d ss v dd v dd v d i dm i d am05540v1 id vg s vd s 90 % vd s 10 % id 90 % vg s on tdel a y-off tf a ll tri s e tcro ss -over 10 % vd s 90 % id vg s (i(t)) on -off tf a ll tri s e - )) concept w a veform for ind u ctive lo a d t u rn-off
STL8N65M5 package mechanical data doc id 019013 rev 3 9/13 4 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack ? specifications, grade definitions and product status are available at: www.st.com. ecopack is an st trademark.
package mechanical data STL8N65M5 10/13 doc id 019013 rev 3 figure 20. powerflat? 5x5 mechanical drawing table 8. powerflat? 5x5 mechanical dimensions dim. mm min. typ. max. a 0.80 0.90 1.0 a1 0 0.02 0.05 a3 0.24 d 4.90 5.0 5.10 e 4.90 5.0 5.10 e2 2.49 2.57 2.64 e 1.22 1.27 1.32 b 0.43 0.51 0.58 c 0.64 0.71 0.79 7267096_rev_f
STL8N65M5 package mechanical data doc id 019013 rev 3 11/13 figure 21. powerflat?(5x5) recommended footprint (mm)
revision history STL8N65M5 12/13 doc id 019013 rev 3 5 revision history table 9. document revision history date revision changes 05-jul-2011 1 first release 07-jul-2011 2 updated figure 1 . 08-aug-2011 3 updated figure 3: thermal impedance . and r thj-pcb value in table 3: thermal data . minor text changes.
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